Search results for "readout [electronics]"
showing 8 items of 18 documents
MuPix8 — Large area monolithic HVCMOS pixel detector for the Mu3e experiment
2019
Abstract The requirements of the ultra thin pixel detectors for the Mu3e experiment at PSI can be achieved by the HVCMOS technology, which allows the design of fast monolithic detectors. The latest nearly full size prototype, MuPix8, has a size of about 1 × 2 cm 2 . The pixel readout circuitry was fully redesigned in comparison to the previous MuPix versions. MuPix8’s readout electronics implement a new concept with two comparators and two different operation modes. One mode uses two threshold voltages for time walk correction, the other is a ramp-ADC. First tests show a detection efficiency of 99.6% for 4 GeV electrons.
Point-to-point readout for the ALICE EMCal detector
2014
Abstract It is anticipated that the LHC will deliver Pb+Pb collisions at a minimum bias interaction rate of about 50 kHz after the second long shutdown of the LHC in 2018. This will be roughly two orders of magnitude greater than the current data recording rate capability of the ALICE experiment. Therefore a major upgrade of the ALICE detector is planned for the next shutdown to enable ALICE to record data at the full Pb+Pb minimum bias interaction rate delivered by the LHC. A new point-to-point readout system for the electromagnetic calorimeter (EMCal) of ALICE has been developed, to replace the legacy readout bus, that essentially accomplishes this goal, and is being installed during the …
The MuPix high voltage monolithic active pixel sensor for the Mu3e experiment
2015
Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay μ → eee. In order to reduce background by up to 16 orders of magnitude, decay vertex position, decay time and particle momenta have to be measured precisely. A pixel tracker based on 50 μm thin high voltage monolithic active pixel sensors (HV-MAPS) in a magnetic field will deliver precise vertex and momentum information. Test beam results like an excellent efficiency of >99.5% and a time resolution of better than 16.6 ns obtained with the MuPix HV-MAPS chip developed for the Mu3e pixel tracker are presented.
An upgraded ATLAS central trigger for 2015 luminosities
2013
The Central Trigger Processor (CTP) is a core unit of the first of three levels that constitute the ATLAS trigger system. Based on information from calorimeter and muon trigger processors as well as from some additional systems it produces the level-1 trigger decision and prompts the read-out of the sub-detectors. The increase in luminosity at the LHC has pushed the CTP operation to its design limits. In order to still satisfy the physics goals of the experiment after the shutdown of the LHC of 2013/2014 the CTP will be upgraded during this period. This article discusses the current Central Trigger Processor, the motivation for the upgrade, and the changes foreseen to meet the requirements …
Synchronization of the distributed readout frontend electronics of the Baby MIND detector
2017
Baby MIND is a new downstream muon range detector for the WGASCI experiment. This article discusses the distributed readout system and its timing requirements. The paper presents the design of the synchronization subsystem and the results of its test.
Equivalence of Open-Loop and Closed-Loop Operation of SAW Resonators and Delay Lines
2019
International audience; Surface acoustic wave (SAW) sensors in the form of two-port resonators or delay lines are widely used in various fields of application. The readout of such sensors is achieved by electronic systems operating either in an open-loop or in a closed-loop configuration. The mode of operation of the sensor system is usually chosen based on requirements like, e.g., bandwidth, dynamic range, linearity, costs, and immunity against environmental influences. Because the limit of detection (LOD) at the output of a sensor system is often one of the most important figures of merit, both readout structures, i.e., open-loop and closed-loop systems, are analyzed in terms of the minim…
A new ATLAS muon CSC readout system with system on chip technology on ATCA platform
2015
The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applicati…
Latest Developments and Results of Radiation Tolerance CMOS Sensors with Small Collection Electrodes
2020
The development of radiation hard Depleted Monolithic Active Pixel Sensors (DMAPS) targets the replacement of hybrid pixel detectors to meet radiation hardness requirements of at least 1.5e16 1 MeV neq/cm2 for the HL-LHC and beyond. DMAPS were designed and tested in the TJ180 nm TowerJazz CMOS imaging technology with small electrodes pixel designs. This technology reduces costs and provides granularity of 36.4x36.4 um2 with low power operation (1 uW/pixel), low noise of ENC < 20 e-, a small collection electrode (3 um) and fast signal response within 25 ns bunch crossing. This contribution will present the latest developments after the MALTA and Mini-MALTA sensors. It will illustrate the imp…